With development of the display technology, people has increasing demand for display quality, and the demand for a panel display apparatus with high picture quality and high resolution becomes more and more common and gets more and more attention of display panel manufacturers.
A thin film transistor (TFT) is a main drive device of a flat display panel, and is directly related to the development direction of a panel display apparatus with high performance. There are various structures of thin film transistor, and there are various materials for manufacturing the corresponding structures of thin film transistor. Both of amorphous silicon and polycrystalline silicon are commonly used materials for preparing the corresponding structures of thin film transistor. However, amorphous silicon has many defects such as low mobility, low stability, etc., which cannot be avoided. By contrast, low temperature polycrystalline silicon (LTPS) has a higher mobility and stability, and the mobility of low temperature polycrystalline is up to dozens or even hundreds times of that of amorphous silicon. Thus, the technology of manufacturing thin film transistors by using material of low temperature polycrystalline silicon has been developed rapidly, and a new generation of liquid crystal display (LCD) or organic light emitting diode (OLED) display derived from LTPS becomes an important display technology. Especially, the OLED display apparatus, due to characteristics of ultra-thin, low power consumption, self-luminous, etc., are much favoured by users.
Although a low temperature polycrystalline silicon thin film transistor has above advantages, in an array substrate of LTPS TFT, in order to achieve continuous drive ability, a storing capacitor (CS) is further needed to be provided. Especially, in a display panel with high resolution, in order to meet the need of driving, a storing capacitor allowed to be charged rapidly is generally needed to be provided for the low temperature polycrystalline silicon thin film transistor.
FIG. 1 shows a sectional view of a structure of an array substrate of LTPS TFT in the prior art. The array substrate comprises a buffer layer 2, an active layer 3, a first insulation layer 4′, a gate 5, a second insulation layer 6′, a source 71, a drain 72, a third insulation layer 8′, a planarization layer 9 and a display electrode 10 which are successively arranged above a base substrate 1. Currently, this structure of array substrate is manufactured by performing eight patterning processes using eight masks. The eight patterning processes include: by using a mask for active layer (a-Si Mask), forming a pattern including the active layer 3 by a first patterning process; by using a mask for storing capacitor (Cs Mask), doping p-Si in a part of the first insulation layer 4′ by a second patterning process to form a pattern including a first plate 11 of the storing capacitor Cs, wherein, the first plate of the storing capacitor Cs is formed by doping through a first ion injection method, but there may be a defect that the storing capacitor discharges slowly because the first plate thereof is formed through the first ion injection method; by using a mask for gate (Gate Mask), forming a pattern including the gate 5 and a second plate 12 of the storing capacitor Cs by a third patterning process, wherein, the second plate of the storing capacitor Cs is formed of gate metal; by using a mask for contact hole (Contact Mask), forming a pattern including contact holes for connecting the source 71 and the drain 72 with the active layer 3 in the second insulation layer 6′ by a fourth patterning process; by using a mask for source and drain (S/D Mask), forming a pattern including the source 71 and the drain 72 by a fifth patterning process; by using a mask for via hole (VIA Mask), forming a pattern including a bridging via hole between the display electrode 10 and the drain 72 in the third insulation layer 8′ by a sixth patterning process; by using a mask for planarization layer (PLN Mask), forming a pattern including a bridging via hole between the display electrode 10 and the drain 72 in the planarization layer 9 by a seventh patterning process and flatting the array substrate, so as to deposit an electrode layer on the flatted array substrate; by using a mask for pixel electrode (ITO Mask), forming a pattern of display electrode 10 by an eighth patterning process.
In view of above, in the prior art, the processes of manufacturing the array substrate comprising LTPS TFT and Cs are complex and include many procedures, resulting in a high produce cost. Meanwhile, because one plate of the storing capacitor is formed by doping, the charging speed of the storing capacitor is affected, resulting that the competitive advantage of LTPS TFT array substrate is reduced.